View ISL85033CRSHEVAL1Z_9074389.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

fn6676 rev 8.00 page 1 of 26 february 17, 2015 fn6676 rev 8.00 february 17, 2015 isl85033 wide v in dual standard buck regulator with 3a/3a continuous output curr ent datasheet the isl85033 is a dual standard buck regulator capable of 3a per channel continuous output current. with an input range of 4.5v to 28v, it provides a high frequency power solution for a variety of point of load applications. the pwm controller in the is l85033 drives an internal switching n-channel power mosfet and requires an external schottky diode to generate the ou tput voltage. the integrated power switch is optimized for excellent thermal performance up to 3a of output current. the pwm regulator switches at a default frequency of 500khz and it can be user programmed or synchronized from 300khz to 2mhz. the isl85033 utilizes peak current mode control to provide flexibility in component selection and minimize solution size. the protection features include overcurrent, uvlo and thermal overload protection. the isl85033 is available in a small 4mmx4mm thin quad flat no-lead (tqfn) pb-free package. related literature ? an1574 ?isl85033dualeval1z wide vin dual standard buck regulator with 3a/3a output current? ? an1585 ?isl85033eval2z (small form) wide vin dual standard buck regulator with 3a/3a output current - short form? ? an1584 ?isl85033eval2z (small form) wide vin dual standard buck regulator with 3a/3a output current - long form? ? an1605 ?ISL85033CRSHEVAL1Z wide vin current sharing standard buck regulator with 6a output current? features ? wide input voltage range from 4.5v to 28v ? adjustable output voltage with continuous output current up to 3a ? current mode control ? adjustable switching freque ncy from 300khz to 2mhz ? independent power-good detection ? selectable in-phase or out-of-phase pwm operation ? independent, sequential, ratiom etric or absolute tracking between outputs ? internal 2ms soft-start time ? overcurrent/short circuit protection, thermal overload protection, uvlo ? boot undervoltage detection ? pb-free (rohs compliant) applications ? general purpose point-of-l oad dc/dc power conversion ?set-top boxes ? fpga power and stb power ? dvd and hdd drives ?lcd panels, tv power ?cable modems figure 1. efficiency vs load, v in = 28v, t a = +25c 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 12v out 1mhz
isl85033 fn6676 rev 8.00 page 2 of 26 february 17, 2015 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 operation initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-on reset and undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output tracking and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 buck regulator overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 boot undervoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 application guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 synchronization control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 buck regulator output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 current sharing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 theory of compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pwm comparator gain fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power stage transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 rectifier selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power derating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
isl85033 fn6676 rev 8.00 page 3 of 26 february 17, 2015 pin configuration isl85033 (28 ld tqfn) top view vin1 phase1 fs nc ss2 pgnd2 boot2 3 4 5 6 18 17 16 15 27 26 25 24 891011 sgnd ss1 pgnd1 vcc phase1 phase2 en1 7 12 19 28 en2 boot1 phase2 vin2 vin2 comp2 fb2 20 23 22 syncout 1 2 comp1 fb1 pgood1 syncin pgood2 14 vin1 13 21 pd pin descriptions pin number symbol pin description 1, 21 comp1, comp2 comp1, comp2 are the output of the error amplifier. 2, 20 fb1, fb2 feedback pin for the regulator. fb is the negative input to the voltage loop error amplifier. comp is the output of the error amplifier. the output voltage is set by an external resistor divider connected to fb. in addition, the pwm regulator?s power-good and undervoltage protection circuits use fb1, fb2 to monitor the regulator output voltage. 3, 19 ss1, ss2 soft-start pins for each controller. the ss1, ss2 pins control the soft-start and sequence of their respective outputs. a single capacitor from the ss pin to ground determines the output ramp rate. see the ? output tracking and sequencing ? on page 16 for soft-start and output tracking/sequencing details. if ss pins are tied to vcc, an internal soft-start of 2ms will be used. maximum c ss value is 100nf. 4, 18 pgnd1, pgnd2 power ground connections. connect directly to the system gnd plane. 5, 17 boot1, boot2 floating bootstrap supply pin for the power mosfet gate driver. the bootstrap capacitor provides the necessary charge to turn on the internal n-channel mosfet. connect an external capacitor from this pin to phase. 6, 7, 15, 16 phase1, phase2 switch node output. it connects the so urce of the internal power mosfet with the external output indu ctor and with the cathode of the external diode. 8, 9, 13, 14 vin1, vin2 the input supply for the power stage of th e pwm regulator and the source for the internal linear regulato r that provides bias for the ic. place a minimum of 10f ceramic capacitance from each vin to gnd and close to the ic for decoupling. 10, 12 en1, en2 pwm controller?s enable inputs. the pwm controllers are held off when the pin is pulled to ground. when the voltage on this pin rises above 2v, the pwm controlle r is enabled. if en1, en 2 pins are driven by an external signal, the minimum off-t ime for en1, en2 should be: where c ss is the soft-start pin capacitor (nf). the isl85033 does not have debouncing to en1, en2 external signals. 11 vcc output of the internal 5v linear regulator. decoup le to pgnd with a minimum of 4.7f ceramic capacitor. this pin is provided only for inte rnal bias of isl85033 (not to be loaded with current over 10ma). en_t_off ? s ?? 10 ? sc ss 2.2nf ? ? =
isl85033 fn6676 rev 8.00 page 4 of 26 february 17, 2015 23 syncout synchronization output. provides a sign al that is the inverse of the syncin signal. 24 syncin connect to an external signal for synchronization from 300khz to 2mhz (negativ e edge trigger). syncin is not allowed to be floating. when syncin = logic 0, phase1 and phase2 are running at 180 out-of-phase. when syncin = logic 1, phase1 and phase2 are running at 0 in-phase. when syncin = an external clock, phase1 and phase2 are running at 180 out-of-phase. external sync frequency applied to the syncin pin shou ld be at least 2.4 x the internal switching frequency setting. 25 sgnd signal ground connections. the exposed pad must be connected to sgnd and soldered to the pcb. all voltage levels are measured with respect to this pin. 26 nc this is a no connection pin. 27 fs frequency selection pin. tie to vcc for 500khz switching frequency. connect a resistor to gnd for adjustable frequency from 300khz to 2mhz. 22, 28 pgood2, pgood1 open-drain power-good ou tput that is pulled to ground when the output voltage is below regulation limits o r during the soft-start interval. there is an internal 5m internal pull-up resistor. pd the exposed pad must be connected to the system gn d plane with as many vias as possible for proper electrical and thermal performance. pin descriptions (continued) pin number symbol pin description
isl85033 fn6676 rev 8.00 page 5 of 26 february 17, 2015 typical application schematics figure 2. dual 3a output (v in range from 4.5v to 28v) figure 3. single 6a output (v in range from 4.5v to 28v) current sharing isl85033 vin1 nc c 2 r 4 comp1 fb1 c 71 en1 r 1 r 2 c 1 v out1 c 9 l1 phase1 boot1 v out1 c 8 68pf 42.2k 470pf 69.8k 8.06k 10nf d 1 7 h b340b 47 f 20 f c 5 r 8 comp2 fb2 r 5 r 6 c 4 v out2 68pf 25.5k 470pf 69.8k 8.06k c 13 l 2 phase2 boot2 c 12 10nf d 2 7 h b340b 47 f en2 3a 3a fs ss1 vcc vin2 ss2 pgood2 pgood1 syncin syncout c 72 10 f vcc vcc vcc v out2 4.7f pgnd1/2 sgnd 27 19 3 22 21 28 15/16 17 12 24 23 4/18 12 26 10 25 11 8/9 13/14 6/7 5 20 isl85033 vin1 nc comp1 fb1 c 71 en1 c 9 l 1 phase1 boot1 c8 10n f d 1 7 h b340b 47 f 20 f c 5 r 8 comp2 fb2 r 5 r 7 r 6 c 4 v out1 0 68pf 42.2k 1nf 34k 8.06k c 13 phase2 boot2 c 12 10nf d 2 7 h b340b 47 f en2 6a fs ss1 vcc vin2 ss2 pgood2 pgood1 syncin syncout c72 10 f vcc 4.7f v out1 v out1 fb2 comp2 fb2 pgnd1/2 sgnd 21 20 1 2 8/9 13/14 27 19 3 22 28 15/16 17 24 23 4/18 12 26 10 25 11 6/7 5 l 2 c ss2 47nf c ss1 47nf
isl85033 fn6676 rev 8.00 page 6 of 26 february 17, 2015 functional block diagram slope comp oscillator ldo 0.8v csa2 ea reference + - comp2 + - vin1 control soft-start monitor voltage fs fault monitor power-on reset monitor thermal monitor +150c epad gnd csa2 + comp2 v cc = 5v gate drive boot uv + - -10% vcc 5m boot2 csa2 gate drive boot uv detection boot refresh control ea 0.8v + - + - control soft-start monitor voltage csa1 monitor fault csa1 + comp1 + - -10% vcc 5m phase1 pgood1 boot1 fb1 en1 en2 phase2 vin2 fb2 comp1 vin1 pgood2 pgnd2 pgnd1 syncout syncin csa1 boot refresh control slope comp ss2 ss1 sgnd vcc vcc vcc vin1 reference detection
isl85033 fn6676 rev 8.00 page 7 of 26 february 17, 2015 ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl85033irtz 850 33irtz -40 to +85 28 ld tqfn l28.4x4 isl85033-12veval3z evaluation board isl85033dualeval1z evaluation board isl85033eval2z evaluation board ISL85033CRSHEVAL1Z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl85033 . for more information on msl please see techbrief tb363 .
isl85033 fn6676 rev 8.00 page 8 of 26 february 17, 2015 absolute maximum rating s thermal information vin1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v phase1/2 to gnd . . . . . . . . . . . . . . . . . . . -7v (<10ns) /-0.3v (dc) to +33v boot1/2 to phase1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v fs to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v syncin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v fb1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +2.95v en1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v pgood1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v comp1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v vcc to gnd short maximum duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s syncout to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v ss1/2 to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 3kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . .2.2kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v latch-up (tested per jesd-78a; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance ? ja (c/w) ? jc (c/w) qfn package ( notes 4 , 5 ) . . . . . . . . . . . . . . 38 3 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c operating temperature range . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 28v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = -40c to +85c, v in = 4.5v to 28v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c parameter symbol test conditions min ( note 8 )typ max ( note 8 )units supply voltage v in voltage range vin 4.5 28 v v in quiescent supply current i q 1.2 2.2 ma v in shutdown supply current i sd en1/2 = 0v 20 45 a v cc voltage v cc v in = 12v; i out = 0ma 4.5 5.1 5.6 v power-on reset vin por threshold rising edge 3.9 4.4 v falling edge 3.2 3.7 v oscillator nominal switching frequency f sw fs pin = vcc 420 500 580 khz resistor from fs pin to gnd = 383k 300 khz resistor from fs pin to gnd = 40.2k 2000 khz fs voltage v fs fs = 100k 780 800 820 mv switching frequency syncin = 600khz 300 khz 1.2mhz syncin 4mhz 600 2000 khz minimum off-time t off 130 ns error amplifier error amplifier transconductance gain gm 125 205 285 a/v fb1, fb2 leakage current v fb = 0.8v 10 100 na current sense amplifier gain r t 0.18 0.21 0.24 v/a reference voltage 0.792 0.8 0.808 v soft-start ramp time ss1, ss2 = v dd 1.5 2.5 3.5 ms soft-start charging current i ss 1.4 2 2.6 a
isl85033 fn6676 rev 8.00 page 9 of 26 february 17, 2015 power-good pg1, pg2 trip level pg to pgood1, pgood2 rise 91 94 % fall 82.5 85.5 % pg1, pg2 propagation delay percent age of the soft-start time 10 % pg1, pg2 low voltage isink = 3ma 100 300 mv enable input en1, en2 leakage current en1/2 = 0v/5v -1 1 a en1, en2 input threshold voltage low level 0.8 v float level 1.0 1.4 v high level 2 v sync input/output syncin input threshold falling edge 1.1 1.4 v rising edge 1.6 1.9 v hysteresis 200 mv syncin leakage current syncin = 0v/5v 10 1000 na syncin pulse width 100 ns syncout phase-shift to syncin measured from rising edge to rising edge, if duty cycle is 50% 180 degree syncout frequency range 600 4000 khz syncout output voltage high isyncout = 3ma v cc - 0.3 v cc -0.08 v syncout output voltage low 0.08 0.3 v fault protection thermal shutdown temperature t sd rising threshold 150 c t hys hysteresis 20 c overcurrent protection threshold ( note 7 ) 4.1 5.1 6.1 a ocp blanking time 60 ns power mosfet high-side r hds i phase = 100ma 75 150 m internal boot1, boot2 refresh low-side r lds i phase = 100ma 1 phase leakage current en1/2 = phase1/2 = 0v 300 na phase rise time t rise v in = 25v 10 ns notes: 6. test condition: v in = 28v, fb forced above regulation point (0.8v), no switch ing, and power mosfet gate charging current not included. 7. established by both current sense amplifier gain test and current sense amplifier output test at i l = 0a. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications t a = -40c to +85c, v in = 4.5v to 28v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c (continued) parameter symbol test conditions min ( note 8 )typ max ( note 8 )units
isl85033 fn6676 rev 8.00 page 10 of 26 february 17, 2015 typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. figure 4. efficiency vs load, t a = +25c, v in = 28v figure 5. efficiency vs load, t a = +25c, f sw = 500khz, v in = 12v figure 6. efficiency vs load, t a = +25c, current sharing 5v out , f sw = 500khz figure 7. power dissipation vs load, t a = +25c, current sharing 5v out , f sw = 500khz figure 8. power dissipation vs load, t a = +85c, current sharing 5v out , f sw = 500khz figure 9. v out regulation vs load, channel 1, t a = +25c, 5v out , f sw = 500khz 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 3.3v out 500khz 9v out 1mhz 12v out 1mhz 1.8v out 300khz 5v out 500khz 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 3.3v out 5v out 40 50 60 70 80 90 100 0123456 output load (a) efficiency (%) 12v in 9v in 28v in 0.0 0.7 1.4 2.1 2.8 3.5 4.2 output load (a) power dissipation (w) 0123456 12v in 9v in 28v in 0.0 0.8 1.6 2.4 3.2 4.0 4.8 output load (a) power dissipation (w) 0123456 12v in 9v in 28v in 4.98 4.99 5.00 5.01 5.02 5.03 5.04 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) output voltage (v) 12v in 28v in 9v in
isl85033 fn6676 rev 8.00 page 11 of 26 february 17, 2015 figure 10. v out regulation vs load, current sharing, t a = +25c, 5v out , f sw = 500khz figure 11. v out regulation vs load, channel 2, t a = +25c, 3.3v out , f sw = 500khz figure 12. output voltage regulation vs v in , channel 1, t a = +25c, 5v out , f sw = 500khz figure 13. output voltage regulation vs v in , current sharing, t a = +25c, 5v out , f sw = 500khz figure 14. output voltage regulation vs v in , channel 2, t a = +25c, 3.3v out , f sw = 500khz figure 15. steady state operation at no load channel 1 typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. (continued) 4.98 4.99 5.00 5.01 5.02 5.03 5.04 output load (a) output voltage (v) 12v in 28v in 0123456 9v in 3.320 3.322 3.323 3.325 3.326 3.328 3.329 0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) output voltage (v) 18v in 12v in 28v in 4.98 4.99 5.00 5.01 5.02 5.03 5.04 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 2a 3a 4.96 4.97 4.98 4.99 5.00 5.01 5.02 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 4a 6a 3.310 3.315 3.320 3.325 3.330 3.335 3.340 0 5 10 15 20 25 30 input voltage (v) output voltage (v) 0a 2a 3a lx1 5v/div v out1 ripple 20mv/div il1 0.1a/div
isl85033 fn6676 rev 8.00 page 12 of 26 february 17, 2015 figure 16. steady state operat ion at no load channel 1 (v in = 9v) figure 17. steady state operation at no load channel 2 figure 18. steady state operation with full load channel 1 f igure 19. steady state operatio n with full load channel 2 figure 20. steady state operation with full load current sharing figure 21. load transient channel 1 typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. (continued) lx1 5v/div v out1 ripple 20mv/div il1 0.2a/div lx2 5v/div v out2 ripple 20mv/div il2 0.1a/div lx1 5v/div v out1 ripple 20mv/div il1 1a/div lx2 5v/div v out2 ripple 20mv/div il2 1a/div lx2 10v/div v out ripple 20mv/div lx1 10v/div v out1 ripple 20mv/div il1 2a/div
isl85033 fn6676 rev 8.00 page 13 of 26 february 17, 2015 figure 22. load transient channel 2 figure 23. soft-start with no load channel 1 figure 24. soft-start with no load channel 2 figure 25. soft-start at full load channel 1 figure 26. soft-start at full load channel 2 f igure 27. soft-discharge shutdown channel 1 typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. (continued) v out2 ripple 20mv/div il2 2a/div en1 5v/div v out1 2v/div il1 0.5a/div pg1 5v/div en2 5v/div v out2 2v/div il2 0.5a/div pg2 5v/div en1 5v/div v out1 2v/div il1 2a/div pg1 5v/div en2 5v/div v out2 2v/div il2 2a/div pg2 5v/div en1 5v/div v out1 1v/div il1 0.5a/div pg 5v/div il1 0.5a/div
isl85033 fn6676 rev 8.00 page 14 of 26 february 17, 2015 figure 28. soft-discharge shutdown channel 2 figur e 29. independent start-up sequencing at no load figure 30. ratiometric start-up sequencing at no load figure 31. absolute start-up sequencing at no load figure 32. steady state operation channel 1 at full load with sync frequency = 4mhz figure 33. steady state operation channel 2 at full load with sync frequency = 4mhz typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. (continued) en2 5v/div v out2 0.5v/div il2 0.5a/div pg 5v/div en1, 2 2v/div v out1 2v/div v out2 2v/div en1, 2 2v/div v out1 2v/div v out2 2v/div v out1 2v/div v out2 2v/div en1, 2 2v/div lx1 10v/div v out1 ripple 20mv/div lx2 10v/div sync 5v/div lx1 10v/div v out2 ripple 20mv/div lx2 10v/div sync 5v/div
isl85033 fn6676 rev 8.00 page 15 of 26 february 17, 2015 figure 34. output short circuit channel 1 figure 35. output short circuit hiccup and recovery for channel 1 figure 36. output short circuit channel 2 figure 37 . output short circuit hiccup and recovery for channel 2 typical performance curves circuit of figure 2 . v in = 12v, v out1 = 5v, v out2 = 3.3v, i out1 = 3a, i out2 = 3a, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. (continued) v out1 2v/div phase1 10v/div il1 2a/div pg1 5v/div v out1 2v/div phase1 10v/div il1 2a/div pg1 5v/div v out2 2v/div phase2 10v/div il2 2a/div pg2 5v/div v out2 2v/div phase2 10v/div il2 2a/div pg2 5v/div
isl85033 fn6676 rev 8.00 page 16 of 26 february 17, 2015 detailed description the isl85033 combines a standard buck pwm controller with integrated switching mosfets. the buck controller drives an internal n-channel mosfet and re quires an external diode to deliver load current up to 3a. a schottky diode is recommended for improved efficiency and performance over a standard diode. the standard buck regulator can operate from an unregulated dc source, such as a battery, with a voltage ranging from +4.5v to +28v. the converter output can be regulated to as low as 0.8v. these features make the isl85033 ideally suited for fpga, set-top boxes, lcd panels, dvd drives, and wireless chipset power applications. the isl85033 employs peak current-mode control loop, which simplifies feedback loop compensation and rejects input voltage variation. external feedback loop compensation allows flexibility in output filter component selection. the regulator switches at a default 500khz and it can be adjusted from 300khz to 2mhz with a resistor from fs to gn d. the isl85033 is synchronizable from 300khz to 2mhz. operation initialization the power-on reset circuitry and enable inputs prevent false start-up of the pwm regulator outp ut. once all input criteria are met, the controller soft starts the output voltage to the programmed level. power-on reset and undervoltage lockout the isl85033 automatically initializes upon receipt of input power supply. the power-on reset (por) function continually monitors v in1 voltage. while below the por threshold, the controller inhibits switching of the internal power mosfet. once exceeded, the controller initializes the internal soft-start circuitry. if v in1 supply drops below their fa lling por threshold during soft-start or operation, the buck regulator is disabled until the input voltage returns. enable and disable when en1 and en2 are pulled low, the device enters shutdown mode and the supply current drops to a typical value of 20a. all internal power devices are held in a high impedance state while in shutdown mode. the en pin enables the controll er of the isl85033. when the voltage on the en pin exceeds it s logic rising threshold, the controller initiates the 2ms soft-start function for the pwm regulator. if the voltage on th e en pin drops below the falling threshold, the buck regulator shuts down. if en1 and en2 pins are driven by an external signal, the minimum off-time for en1 and en2 should be: where c ss is the soft-start pin capacitor (nf). the isl85033 does not have debouncing to the en1 and en2 external signals. power-good pg is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the fb pin. pg is actively held low when en is low and during the buck regulator soft-start period. after the soft-start period terminates, pg becomes high impedance as long as the output voltage (monitored on the fb pin) is ab ove 90% of the nominal regulation voltage set by fb. when v out drops 10% below the nominal regulation voltage, the isl85033 pulls pg low. any fault condition forces pg low until the fault cond ition is cleared by attempts to soft-start. there is an internal 5m internal pull-up resistor. output voltage selection the regulator output voltage is easily programmed using an external resistor divider to scale v out relative to the internal reference voltage. the scaled voltage is applied to the inverting input of the error amplifier; refer to figure 38 . the output voltage programming resistor, r 2 , depends on the value chosen for the feedback resistor, r 3 , and the desired output voltage, v out , of the regulator. equation 2 describes the relationship between v out and resistor values. r 3 is often chosen to be in the 1k to 10k range. if the desired output voltage is 0.8v, then r 3 is left unpopulated and r 2 is 0 . output tracking and sequencing the output tracking and sequen cing between channels can be implemented by using the ss1 and ss2 pins. figures 39 , 40 and 41 show several configurations for output tracking/sequencing for a 2.5v and 1.8v application. independent soft-start for each channel is shown in figure 39 and measured in figure 29 . the output ramp-time for each channel (t ss ) is set by the soft-start capacitor (c ss ) as shown by equation 3 . the maximum c ss value is recommended not to exceed 100nf. ratiometric tracking is achieved in figure 40 by using the same value for the soft-start capacitor on each channel; it is measured in figure 30 . by connecting a feedback network from v out1 to the ss2 pin with the same ratio that sets v out2 voltage, absolute tracking shown in figure 41 is implemented. the measurement is shown in figure 31 . if the output of channel 1 is shorted to gnd, it will enter overcurrent hiccup mode, ss2 will be pulled low through the added resistor between v out1 and ss2 and this will force channel 2 into hiccup as well. if the output of channel 2 is en_t_off ? s ?? 10 ? sc ss 2.2nf ? ? = (eq. 1) r 2 v out ? 0.8 ? r 3 0.8 ? ? C = (eq. 2) r 2 r 3 0.8v ea reference + - v out figure 38. external resistor divider fb c ss ? f ?? 2.5*t ss s ?? = (eq. 3)
isl85033 fn6676 rev 8.00 page 17 of 26 february 17, 2015 shorted to gnd with v out1 in regulation, it will enter overcurrent hiccup mode with a very short hiccup waiting time. the reason is that v out1 is still in regulation and can pull up ss2 very quickly via the resistor added between v out1 and ss2. figure 42 illustrates output sequenci ng. when en1 is high and en2 is floating, out1 comes up first and out2 will not start until out1 > 90% of its regulation point. if en1 is floating and en2 is high, out2 comes up first an d out1 will not start until out2 > 90% of its regulation point. if en1 = en2 = high, out1 and out2 come up at the same time. please refer to table 1 for conditions related to figure 42 (output sequencing). protection features the isl85033 limits th e current in all on-c hip power devices. overcurrent protection limits the current on the two buck regulators and internal ldo for v cc . buck regulator overcurrent protection during pwm on-time, current th rough the internal switching mosfet is sampled and scaled through an internal pilot device. the sampled current is compared to a nominal 5a overcurrent limit. if the sampled current exceeds the overcurrent limit reference level, an internal overcurrent fault counter is set to 1 and an internal flag is set. the internal power mosfet is immediately turned off and will not be turned on again until the next switching cycle. the protection circuitry continues to monitor the current and turns off the internal mosfet as described. if the overcurrent condition persists for 17 sequential clock cycles, the overcurrent fault counter overflows indicating an overcurrent fault condition exists. the regulator is shutdown and power-good goes low. the buck controller attempts to recover from the overcurrent condition after waiting 8 soft -start cycles. the internal overcurrent flag and counter are re set. a normal soft-start cycle table 1. output sequencing en1 en2 v out1 v out2 note high floating first after v out1 >90% floating high after v out2 > 90% first high high same time as v out2 same time as v out1 floating floating not allowed ss2 ss1 v out1 c1 22nf c2 47nf c 3 c 4 v out2 isl85033 5.0v 3.3v figure 39. independent start-up ss2 ss1 v out1 c 1 22nf c 3 c 4 v out2 isl85033 5.0v 3.3v figure 40. ratiometric start-up c 2 22nf ss2 ss1 v out1 c 1 47nf c 3 c 4 v out2 r 2 8.06k r 1 25.5k 5.0v 3.3v figure 41. absolute start-up isl85033 ss2 ss1 v out1 c 1 22nf c 3 c 4 v out2 5.0v 3.3v c 2 22nf en1 en2 figure 42. output sequencing isl85033
isl85033 fn6676 rev 8.00 page 18 of 26 february 17, 2015 is attempted and normal oper ation continues if the fault condition has cleared. if the overcurrent fault counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats. thermal overload protection thermal overload protection limits maximum junction temperature in the isl85033. when the junction temperature (t j ) exceeds +150c, a thermal sensor sends a signal to the fault monitor. the fault monitor commands the buck regulator to shutdown. when the junction temperature has decreased by 20c, the regulator will attempt a normal soft-start sequence and return to normal operation. for continuous operation, the +125c junction temperature rating should not be exceeded. boot undervoltage protection if the boot capacitor voltage falls below 2.5v, the boot undervoltage protection circuit will pull the phase pin low through a 1 switch for 400ns to recharge the capacitor. this operation may arise during long periods of no switching as in no load situations. application guidelines operating frequency the isl85033 operates at a de fault switching frequency of 500khz if fs is tied to v cc . tie a resistor from fs to gnd to program the switching frequency from 300khz to 2mhz, as shown in equation 4 . [minimum on-time of 150ns (typical) in conjunction with the input an d output voltage should be considered when selecting the maximum operating frequency]. where t is the switching period in s. synchronization control the frequency of operation can be synchronized up to 2mhz by an external signal applied to the syncin pin. the falling edge on the syncin triggers the rising edge of phase1/2. the switching frequency for each output is half of the syncin frequency. output inductor selection the inductor value determines the converter?s ripple current. choosing an inductor current re quires a somewhat arbitrary choice of ripple current, ? i. a reasonable starting point is 30% of total load current. the inductor value can then be calculated using equation 5 : increasing the value of inductance reduces the ripple current and thus ripple voltage. however, the larger inductance value may reduce the converter?s response time to a load transient. the inductor current rating should be such that it will not saturate in overcurrent conditions. buck regulator output capacitor selection an output capacitor is required to filter the inductor current. the output ripple voltage and transien t response are 2 critical factors when considering output capacitance choice. the current mode control loop allows the usage of low esr ceramic capacitors and thus smaller board layout. electr olytic and polymer capacitors may also be used. additional consideration applies to ceramic capacitors. while they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter applic ation, these cond itions do not reflect reality. as a result, the actual capacitance may be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so that this effect can be eas ily accommodated. the effects of ac voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. the result of these considerations can easily result in an effective capacitance 50% lower than the rated value. nonetheless, they are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr): where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: r fs k ? ?? 122k ? ? t ? 0.17 ? s ? C = (eq. 4) figure 43. r fs selection vs f sw 300 200 100 0 500 750 1000 1250 1500 1750 2000 f sw (khz) r fs (k) l v in v out C f sw ? i ? ------------------------------- - v out v in --------------- - ? = v outripple ? i 8 ? f sw ? c out ------------------------------------ - = (eq. 6) v outripple ? i*esr = (eq. 7)
isl85033 fn6676 rev 8.00 page 19 of 26 february 17, 2015 regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. equation 8 determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. for an overshoot of 5%, the equation becomes equation 9 : figure 44 shows the relationship of c out and % overshoot at three different output voltages. l is assumed to be 7h and i out is 3a. current sharing configuration in current sharing configuration, fb1 is connected to fb2, en1 to en2, comp1 to comp2 and v out1 to v out2 as shown in figure 3 on page 5 . as a result, the equivalent g m doubles its single channel value. since the two channels are out-of-phase, the frequency will be 2x the channel switching frequency. ripple current cancellation will reduce the ripple current seen by the output capacitors and thus lower the ripple voltage. this results in the ability to use less capacitance than would be required by a single phase design of similar ra ting. ripple current cancellation also reduces the ripple current seen at the input capacitors. input capacitor selection to reduce the resulting input voltage ripple and to minimize emi by forcing the very high frequency switching current into a tight local loop, an input capacitor is required. the input capacitor must have adequate ripple current rating, which can be approximated by equation 10 . if capacitors other than mlcc are used, attention must be paid to ripple and surge current ratings. where d = v o /v in the input ripple current is graphically represented in figure 45 . a minimum of 10f ceramic capaci tance is required on each vin pin. the capacitors must be as close to the ic as physically possible. additional capacitance may be used. loop compensation design the isl85033 uses a constant fr equency current mode control architecture to achieve simplifi ed loop compensation and fast loop transient response. the compensator schematic is shown in figure 47 . as mentioned in the c out selection, isl85033 allows the usage of low esr output capacitor. choice of the loop bandwidth f c is somewhat arbitrary but should not exceed 1/4 of the switching frequency. as a starting point, the lower of 100khz or 1/6 of the switching frequency is reasonable. the following equations determine initial component values for the compensation, allowing the designer to make the selection with minimal effort. further detail is provided in ? theory of compensation ? on page 20 to allow fine tuning of the compensator. compensation resistor r 1 is given by equation 11 : which, when applied to the isl85033 becomes: where c o is the output capacitor value [f], f c = loop bandwidth [khz] and v o is the output voltage [v]. compensation capacitors c 1 [nf], c 2 [pf] are given by equation 13 : where i o [a] is the output load current, r 1 ( ) and r c ( ) is the esr of the output capacitor c o . (eq. 8) c out i out 2 * l v out 2 * v outmax v out ? ?? 2 1 ? C --------------------------------------------------------------- ----------------------------- = c out i out 2 * l v out 2 * 1.05 ? 2 1 ? C ----------------------------------------------------- = (eq. 9) figure 44. c out vs overshoot v outmax /v out v outmax /v out c out (f) 1.02 1.04 1.06 1.08 1.10 80 60 40 20 0 3.3v out 5v out 12v out i rms i o ------------ dd 2 C = (eq. 10) figure 45. i rms /i o vs duty cycle duty cycle (d) i rms /i o 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 r 1 2 ? f c v o c o r t g m v fb ----------------------------------- = (eq. 11) r 1 k ? ?? 0.008247 ? f c ? v o ? c o = (eq. 12) (eq. 13) c 1 c o v o 10 ?? 3 ? ? i o r 1 ? ----------------------------------------- c 2 c o r c 10 ?? 6 ? ? r 1 ----------------------------------------- = , =
isl85033 fn6676 rev 8.00 page 20 of 26 february 17, 2015 example: v o = 5v, i o = 3a, f sw = 500khz, f c = 50khz, c o =47f/r c = 5m , then the compensation resistance r 1 =96k . the compensation capacitors are: c 1 = 815pf, c 2 = 2.5pf (there is approximately 3pf parasitic capacitance from v comp to gnd; therefore, c 2 is optional). theory of compensation the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. the inductor is not cons idered as a state variable for current mode control and the sy stem becomes a single order system. it is much easier to desi gn a compensator to stabilize the voltage loop than vo ltage mode control. figure 46 shows the small signal model of the synchronous buck regulator. pwm comparator gain f m the pwm comparator gain f m for peak current mode control is given by equation 14 : where s e is the slew rate of the slope compensation and s n is given by equation 15 . where r t is transresistance and is the product of the current sensing resistance and gain of the current amplifier in current loop. current sampling transfer function h e (s) in current loop, the current sign al is sampled every switching cycle. equation 16 shows the transfer function: where q n and ? n are given by . power stage transfer functions transfer function f 1 (s) from control to output voltage is calculated in equation 17 : where transfer function f 2 (s) from control to inductor current is given by equation 18 : where current loop gain t i (s) is expressed as equation 19 : the voltage loop gain with open current loop is calculated in equation 20 : the voltage loop gain with curre nt loop closed is given by equation 21 : where is the feedback voltage of the voltage error amplifier. if t i (s)>>1, then equation 21 can be simplified as shown in equation 22 : equation 22 shows that the system is a single order system, which has a single pole located at before the half switching frequency. therefore, a simple type ii compensator can be easily used to stabilize the system. d i l i in l + 1:d + l i co rc ro -av(s) d v comp fm he(s) + t k v o t(s) i l + 1:d + co rc ro -av(s) r t fm he(s) t i (s) t v (s) ^ v in ^ ^ ^ ^ figure 46. small signal mo del of synchronous buck regulator ^ ^ v in d ^ f m d ? v ? comp ------------------- - 1 s e s n + ?? t s -------------------------------- == (eq. 14) s n r t v in v o C l ---------------------- - = (eq. 15) h e s ?? s 2 ? n 2 ------ - = s ? n q n --------------- 1 ++ (eq. 16) q n 2 ? -- - C = ? n ? f s = = ? f 1 s ?? v ? o d ? ------ v in 1 s ? esr ----------- - + s 2 ? o 2 ------ - s ? o q p --------------- 1 ++ -------------------------------------- - == (eq. 17) ? esr 1 r c c o -------------- - q p r o c o l ------ - ? o 1 lc o -------------- - = ? ? , = f 2 s ?? i ? o d ? ---- v in r o r l + -------------------- - 1 s ? z ------ + s 2 ? o 2 ------ - s ? o q p --------------- 1 ++ -------------------------------------- - == (eq. 18) ? z 1 r o c o -------------- - = t i s ?? r t f m f 2 s ?? h e s ?? = (eq. 19) t v s ?? kf m f 1 s ?? a v s ?? = (eq. 20) l v s ?? t v s ?? 1t i s ?? + ----------------------- - = (eq. 21) k v fb v o ---------- - v fb , = l v s ?? v fb v o ---------- - r o r l + r t -------------------- - 1 s ? esr ----------- - + 1 s ? p ------ - + --------------------- - a v s ?? h e s ?? ---------------- ? p 1 r o c o -------------- - ? , = (eq. 22) ? p
isl85033 fn6676 rev 8.00 page 21 of 26 february 17, 2015 figure 47 shows the type ii compensator and its transfer function is expressed as equation 23 : where: the compensator design goal is: high dc gain loop bandwidth f c : gain margin: >10db phase margin: 40 the compensator design procedure is shown in equation 25 : put one compensator pole at zero frequency to achieve high dc gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. the loop gain t v (s) at crossover frequency of f c has unity gain. therefore, the compensator resistance r 1 is determined by equation 26 : where g m is the transconductance of the voltage error amplifier, typically 200a/v. compensator capacitor c 1 is then given by equation 27 : example: v in = 12v, v o = 5v, i o = 3a, f sw = 500khz, c o = 22f (derated value over voltage, temperature)/5m , l = 5.6h, g m = 200s, r t = 0.21, v fb =0.8v, s e = 1.1 ? 10 5 v/s, s n =3.4 ? 10 5 v/s, f c = 80khz, then compen sator resistance r 1 =72k . put the compensator zero at 6.6khz (~1.5x c o r o ), and put the compensator pole at esr zero, which is 1.45mhz. the compensator capacitors are: c 1 = 470pf, c 2 = 3pf (there is appr oximately 3pf parasitic capacitance from v comp to gnd; therefore, c 2 is optional). figure 48a shows the simulated voltage loop gain. it is shown that it has 80khz loop bandwidth with 69 phase margin and 15db gain margin. optional addition phase boost can be added to the overall loop response by using c 3 . rectifier selection current circulates from ground to the junction of the external schottky diode and the inductor when the high-side switch is off. as a consequence, the polarity of the switching node is negative with respect to ground. this vo ltage is approximately -0.5v (a schottky diode drop) during the off-time. the rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. the power dissipation when the schottky diode conducts is expressed in equation 28 : where: the v d is the voltage drop of the schottky diode. selection of the schottky diode is critical in terms of the high temperature reverse bias leakage current, wh ich is very dependent on v in and exponentially increasing with temperature. due to the nature of - + r 1 v ref v fb vo gm v comp c 2 - + c 1 v ref v fb vo v comp figure 47. type ii compensator c 3 r 2 r 3 a v s ?? v ? comp v ? fb ------------------- - g m c 1 c 2 + -------------------- - 1 s ? cz1 ------------ - + ?? ?? 1 s ? cz2 ------------ - + ?? ?? s1 s ? cp --------- - + ?? ?? --------------------------------------------------------- = = (eq. 23) ? cz1 1 r 1 c 1 -------------- - ? cz2 1 r 2 c 3 -------------- - = ? cp ? c 1 c 2 + r 1 c 1 c 2 ---------------------- - = , = (eq. 24) 1 4 -- - to 1 10 ------ ?? ?? f sw put compensator zero ? cz1 1to3 ?? 1 r o c 0 -------------- - = r 1 2 ? f c v o c o r t g m v fb ----------------------------------- = (eq. 26) c 1 1 r 1 ? cz ----------------- c 2 1 2 ? r 1 f esr ------------------------ - = , = (eq. 27) 100 1?10 3 1?10 4 1?10 5 1?10 6 -30 -15 0 15 30 45 60 gain (db) figure 48a. -20 0 20 40 60 80 100 phase () 100 1?10 3 1?10 4 1?10 5 1?10 6 figure 48b. p d w ?? i out v d 1 v out v in --------------- - C ?? ?? ?? ?? = (eq. 28)
isl85033 fn6676 rev 8.00 page 22 of 26 february 17, 2015 reverse bias leakage vs temper ature, the diode should be carefully selected to operate in the worst case circuit conditions. catastrophic failure is possible if the diode chosen experiences thermal runaway at elevated temperatures. refer to application notes for an1574 , an1605 , an1584 diode selection listed on page 1 . power derating characteristics to prevent the isl85033 from exceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by equation 29 : where pd is the power dissipated by the regulator and ja is the thermal resistance from the junc tion of the die to the ambient temperature. the junction temperature, t j , is given by equation 30 : where t a is the ambient temperature. for the qfn package, the ja is +38c/w. the actual junction temperature should not exceed the absolute maximum junction temperature of +125c when considering the thermal design, (consider the thermal needs of the rectifier diode). the isl85033 delivers full current at ambient temperatures up to +85c if the thermal impedance from the thermal pad maintains the junction temperat ure below the thermal shutdown level, depending on the input voltage/output voltage combination and the switching frequency. the device power dissipation must be reduced to maintain the junction temperature at or below th e thermal shutdown level. figure 49 illustrates the power derating versus ambient temperature for the isl85033 evaluation kit. note that the evaluation kit derating curve is based on total circuit dissipation, not ic dissipation alone. layout considerations layout is very important in high frequency switching converter designs. with power devices switching efficiently between 100khz and 600khz, the resultin g current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit board design minimizes these voltage spikes. as an example, consider the turn-off transition of the upper mosfet. prior to turn-off, the mosfet is carrying the full load current. during turn-off, current stops flowing in the mosfet and is picked up by the schottky diode. any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components and short, wide traces minimizes the magnitude of voltage spikes. there are two sets of critical components in the isl85033 switching converter. the switch ing components are the most critical because they switch large amounts of energy and therefore tend to generate large amounts of noise. next are the small signal components which connect to sensitive nodes or supply critical bypass curr ent and signal coupling. a multilayer printed circuit board is recommended. figure 50 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, (usually a middle layer of the pc board) for a ground plane and make all critical component gr ound connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminals to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. in order to dissipate heat generated by the internal ldo and mosfet, the ground pad should be connected to the internal ground plane through at least four vias. this allows the heat to move away from the ic and also ties the pad to the ground plane through a low impedance path. the switching compon ents should be placed close to the isl85033 first. minimize the leng th of the connections between the input capacitors, c in , and the power switches by placing them nearby. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. position the output inductor and output capacitors between the upper and schottky diode and the load. the critical small signal components include any bypass capacitors, feedback components, and compensation components. place the pwm converter compensation components close to the fb and comp pins. the feedback resistors should be located as close as possible to the fb pin with vias tied straight to the ground plane as required. t rise pd ??? ja ?? = (eq. 29) t j t a t rise + ?? = (eq. 30) 0 10 20 30 40 50 60 70 80 90 100 110 120 0123456789101112 isl85033eval1zb evaluation board maximum ambient temperature (c) total power dissipation (w) ? ja = +38c/w figure 49. power derating curve
isl85033 fn6676 rev 8.00 page 23 of 26 february 17, 2015 isl85033 d1 cout1 fb2 cboot vin1 vout1 fb1 comp1 comp2 l2 lx2 trace cin1 cin2 cout2 vout2 d2 cboot vout2 vin2 lx1 trace l1 sl85033 . . . . . . . . . ... . . . . . . vias figure 50. printed circuit board power planes and islands
isl85033 fn6676 rev 8.00 page 24 of 26 february 17, 2015 revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change february 17, 2015 fn6676.8 page 21, paragraph below equation 27, changed ?co = 220f/5m ...? to "co = 22f (derated value over voltage, temperature)/5m ... april 17, 2014 fn6676.7 on page 16 in the "output tracking and se quencing" changed the sentence "maximum css value is 50nf" to "t he maximum css value is recommended not to exceed 100nf". figure 39 on page 17, changed c1 from 0.1f to 22nf and c2 from 0.2f to 47nf. figure 40 on page 17, changed the value of both c1 and c2 to 22nf each. figure 41 on page 17, changed c1 value to 47nf. figure 42 on page 17, changed c1 and c2 value to 22nf each. on page 18 in the operating frequency chapter, after the sentence "tie a resistor from fs to gnd to program the switching frequency from 300khz to 2mhz, as shown in equa tion 4." added : "minimum on-time of 150ns (typical) in conjunction with input and output voltage should be considered when selecting the maximum operating frequency". november 2, 2011 fn6676.6 in the ?pin descriptions? on pa ge 3, added the following to end of en1, en2 description: "if en1, en2 pins are driven by an external sign al, the minimum off-time for en1, en2 should be: where css is the soft-start pin capacitor (nf). isl85033 does not have debouncing to en1, en2 external signals." in ?enable and disable? on page 16, adding the following: "if en1, en2 pins are driven by an external sign al, the minimum off-time for en1, en2 should be: where css is the soft-start pin capacitor (nf). isl85033 does not have debouncing to en1, en2 external signals." adding the following after equation 3 on page 16: "maximum css value is 50nf". in the ?pin descriptions? on page 3, added the following to the end of ss1, ss2 description: "maximum css value is 50nf". october 7, 2011 fn6676.5 in ?absolute maximum ratings? on page 8, changed: phase1/2 to gnd . . . . .-0.3v to +33v to: phase1/2 to gnd . . . . .-7v (<10ns) /-0.3v (dc) to +33v september 14, 2011 fn6676.4 in the ?pin descriptions? on page 4, fo r ?syncin?, replaced ?set the internal switching frequency 20% lower than the external sync frequency applied to the syncin pin" with "external sync frequency applied to the syncin pin should be at least 2.4 times the internal switching frequency setting" august 9, 2011 on page 8, changed parameter name from ?syncronization frequency? to ?switching frequency?. april 5, 2011 fn6676.3 converted to new template updated intersil trademark statement at bottom of page 1 per directive from legal. page 2 in the pin table definition, please add the followi ng sentence to the pin 11 (vcc) description after ?output of the internal 5v linear regulator. decouple to pgnd with a minimum of 4.7 f ceramic capacitor.? ?this pin is provided only for internal bias of is l85033 (not to be loaded with current over 10ma).? page 8 all absolute max ratings that are ?5.5? should be changed to ?5.9? october 15, 2010 fn6676.2 added the following sentence to the ?s yncin? description in the ?pin descriptions? table on page 4: ?set the internal switching frequency 20% lower than the external sync fr equency applied to the syncin pin.? added the following sentence to ?synchronization control? on page 18: ?the switching frequency for each output is half of the syncin frequency.? revised tape and reel note in ?ordering information? on page 7 from: ?add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications? to: ?add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications? this is in order to delineate all tape and reel options. en_t_off ? s ?? 10 ? sc ss 2.2nf ? ? = en_t_off ? s ?? 10 ? sc ss 2.2nf ? ? =
fn6676 rev 8.00 page 25 of 26 february 17, 2015 isl85033 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2010-2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support september 14, 2010 corrected eq. 2 on page 16 from: to: revised preceding paragraph from: ?the output voltage programming resistor, r 3 , depends on the value chosen for the feedback resistor, r 2 , and the desired output voltage, v out , of the regulator. equation 2 describes the relationship between v out and resistor values. r 2 is often chosen to be in the 1k to 10k range.? to: ?the output voltage programming resistor, r 2 , depends on the value chosen for the feedback resistor, r 3 , and the desired output voltage, v out , of the regulator. equation 2 describes the relationship between v out and resistor values. r 3 is often chosen to be in the 1k to 10k range.? july 21, 2010 fn6676.1 changed min/max for ?soft-start ch arging current? on page 8 from 1.5/2.5a to 1.4/2.6a july 18, 2010 fn6676.0 initial release. revision history (continued) the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. (continued) date revision change r 3 r 2 x0.8v v out 0.8v C ---------------------------------- = r 2 v out ? 0.8 ? r 3 0.8 ? ? C =
isl85033 fn6676 rev 8.00 page 26 of 26 february 17, 2015 package outline drawing l28.4x4 28 lead thin quad flat no-lead plastic package rev 0, 9/06 typical recommended land pattern detail "x" top view bottom view notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to amse y14.5m-1994 . 4. bottom side pin#1 id is diepad chamfer as shown. 5. tiebar shown (if present) is a non-functional feature. pin 1 index area 4 . 00 0 ~ 0 . 05 5 0 . 10 pin #1 index area chamfer 0 . 400 x 45 2 . 50 2 . 50 3 . 20 a package boundary 4 . 00 0 . 40 0 . 20 0 . 05 0 . 40 0 . 20 ref 0 . 00 - 0 . 05 see detail x'' seating plane (28x 0 . 60) (0 . 40) (28x 0 . 20) (2 . 50) (2 . 50) (3 . 20) (3 . 20) 0 . 4 x 6 = 2.40 ref 3 . 20 0 . 4 x 6 = 2 . 40 ref max. 0 . 80 (0 . 40) b side view c c 0 . 20 ref 0 . 08 c 0 . 10 c 0 . 10 m c a b 2x 14 8 7 1 28 22 21 15

▲Up To Search▲

Price & Availability of ISL85033CRSHEVAL1Z

	To Download ISL85033CRSHEVAL1Z Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .